For building an integrated circuit operating with desired action, it is necessary to fabricate many active devices on a single semiconductor substrate. Various kinds of devices with different functions, such as transistors, resistors and capacitors, are formed together. Today, we usually build hundreds of thousands of semiconductor devices on a single chip. Each of the devices on the substrate must be electrically isolated from the others to ensure their individual function, and, specific devices must be electrically interconnected so as to implement the whole desired circuit function.
In order to construct the interconnection and contact among all the active devices, a metallization process is employed. At an early stage, single layer metallization process provides all the designed connection. But, as the integrated circuit technology trend towards increase of the integration and decrease of the device size, the surface of the chip cannot provide enough area to build all the interconnects needed. It must be designed more than one level of interconnects. The multilevel-interconnect technology is thus developed to meet this demand.
In the development of interconnect technology, as the tendency is scaling down of the device, interconnect delay becomes the performance barrier for high-speed integrated circuits (IC's). The increased interconnect delay will reduce device speed and exaggerate the problem of high cross talk and power dissipation. Low resistivity interconnecting material and low dielectric constant insulator are therefore desired to reduce the increased interconnect delay. In the creation of metal interconnect lines and contact plugs or via plugs, copper is generally the preferred conductive material due to its low resistivity and high electromigration resistance. However, the application of copper suffers from some problems. Copper readily diffuses into commonly used dielectric material such as silicon oxide and oxygen-containing polymer. This can lead to severe corrosion of the copper and the dielectric material for the copper combining with oxygen. The corrosion may result in loss of adhesion, delamination, void, and ultimately a catastrophic failure of the component. A barrier layer is therefore required for copper manufacture process to prevent copper form diffusion.
Another considerable problem of copper manufacture is the effect of copper grain size in narrow interconnects, which has been studied as the semiconductor technology trends to increase the wafer integration and reduce the device dimension. It has been found that, as the ratio of the line width to the grain size decreases, the mean time to failure (MTTF) decreases to minimum and then increases exponentially, and the electromigration induced failure increases continuously. That means, fine grain structure of copper formed for highly integrated devices degrades both the electromigration lifetime and the mean time to failure (MTTF). To deal with such a situation, an electroplating process is employed for copper manufacture due to the relatively large grain structure of the electroplated copper.
In the applications of electroplating technique of copper, a copper seed layer is generally needed on the diffusion barrier layer for landing the electroplated copper. The microstructure of the electroplated copper is highly dependent on the characteristics of the underlying barrier and seed layer. Previous studies have reported on the impact on electromigration of copper films of (111) and (200) textured crystallographic orientation. These study has found that the electromigration lifetime of (111)-oriented copper film is much longer (about four times) than that of the (200)-oriented copper film under equal conditions of activation energy. This makes the copper manufacture face another problem about the poor (111)-oriented texture of copper on the conventional barrier material of titanium nitride, which is widely used in the aluminum barrier and has an advantage of good step coverage.
For getting good (111)-oriented texture of copper to achieve the desired performance, technology using another material for copper barrier is developed. A double film of tantalum and tantalum nitride is adopted to be the copper barrier layer because high wetting and highly (111)-oriented texture of copper film can then be obtained thereon. However, as the integration is continuously increased and the device dimension scaled down, the sputtered tantalum and tantalum nitride barrier film suffers from its poor step coverage. As the aspect ratio is raised in the highly integrated process, that can cause the device fail. A better barrier manufacture process is still required.